Backside Power Meets CFET: The Fabrication Steps Behind Smaller Logic Cells

Stacking a device changes how engineers reach it

A conventional complementary logic gate places n-type and p-type transistors beside each other. Stacking them can reduce the area occupied by that pair, but their connections do not disappear. Imagine placing two workshops on separate floors while keeping every delivery at street level. The saved ground area is useful only if the lifts, stairs, and utilities fit. In a chip, the equivalents are contacts, vias, dielectric separators, and metal routes. Their dimensions can determine whether a smaller transistor actually produces a smaller usable circuit.

Imec’s 2023 process discussion describes monolithic CFETs as a structure patterned from one vertically arranged semiconductor stack. Its experimental path separated the challenge into increasingly complex test vehicles, including unipolar structures before complete complementary arrangements. This matters when reading a headline about a functional device. Demonstrating the upper and lower transistor separately answers a different question from connecting both into a stable logic cell. Neither result alone establishes the defect rate, manufacturable process window, or economic yield of a processor containing billions of devices.

The important 2026 result sits beneath the lower transistor

In its September 7, 2026 update, imec reports a backside-contact experiment presented at the 2026 Symposium on VLSI Technology and Circuits. On a monolithic CFET test vehicle, the lower p-type device’s access resistance fell from 1,753 to 378 ohm-micrometres relative to the reported conventional scheme. Device survival increased from 45% to 85%. Those are test-vehicle comparisons, not a fivefold speedup for a complete chip. The revised isolation scheme helps prevent the substrate from seeding unwanted source-and-drain growth.

The units deserve attention. Resistance multiplied by device width allows researchers to compare contacts across different transistor widths. A resistance of 378 ohm-micrometres does not mean every physical contact is a 378-ohm resistor. Actual resistance depends on the relevant width and the extraction method. Nor is survival yield interchangeable with whole-wafer processor yield. A successful lower transistor remains one necessary element among many. Engineers must still ask whether upper devices, interconnects, and threshold-voltage distributions remain acceptable after the complete sequence.

A contact also becomes harder to improve as its available area shrinks. In a simple uniform model, resistance increases when the conducting cross-section decreases, but real nanoscale contacts add interface barriers and current crowding. A lower measured resistance can therefore reflect several simultaneous improvements rather than one material replacement. To compare process changes, researchers need extraction structures that separate contact access from channel behavior. Repeating measurements at different gate voltages and temperatures can help expose whether the limiting mechanism has changed, although a complete interpretation requires an appropriate device model.

Why contact resistance consumes a logic circuit’s margin

Consider an illustrative circuit drawing 0.1 milliamperes through an extra 100 ohms of series resistance. Ohm’s law gives a 10-millivolt drop. This is a deliberately simplified example, unrelated to imec’s particular transistor dimensions. Its point is that a seemingly small parasitic voltage subtracts directly from the voltage available to charge a node or drive a channel. If the circuit already operates at low supply voltage, several such losses can consume an appreciable fraction of its switching margin.

The heating penalty follows a different dependence: current squared times resistance. Doubling current quadruples resistive dissipation if resistance stays fixed. Designers therefore cannot simply compensate for every weak contact by demanding more current. They must balance switching delay, local temperature, electromigration, and supply noise. Delivering power from the backside can free frontside routing space, but it also introduces its own vertical path and its own mechanical requirements. Useful comparisons include the complete distribution network, rather than just one shortened signal wire.

A good material can still arrive at the wrong process step

Fabrication is constrained by order. A later high-temperature treatment may improve one interface while damaging a layer already completed below it. An aggressive etchant may remove a sacrificial film cleanly in an isolated sample yet attack another material inside the full stack. Engineers therefore evaluate a process module both for its local performance and for its compatibility with all earlier and later modules. This is why a convincing cross-sectional microscope image is valuable but insufficient: electrical measurements must show that the intended interfaces actually function.

The same 2026 imec update describes an intermediate placement of dipole-forming material within a gate dielectric stack. Its reported threshold-voltage shift was about 30 millivolts in accessible upper n-type devices on a CFET test vehicle. The experimental scope is narrow and explicit. The general engineering question is broader: can threshold control be introduced without a damaging thermal treatment or patterning step? Logic libraries need several transistor strengths and leakage levels, so a process that produces only one attractive device setting may still leave circuit designers with too few choices.

The circuit must survive its own smaller floorplan

Reporting its 2025 design-technology co-optimization work on February 26, 2026, imec considered how monolithic CFET standard cells might extend through successive proposed logic generations. The work combines circuit-level exploration with experimental progress on a key isolation module; its scaling scenarios are not evidence that those future nodes are already manufactured. The practical lesson is that a transistor architecture needs a route through several generations. Introducing an expensive fabrication sequence for one short-lived density improvement would be a difficult industrial proposition.

One useful independent test is to shrink a candidate cell while holding the surrounding requirements fixed. Can signals still reach every pin? Does the power rail obstruct the shortest route? Are there enough legal locations for a vertical connection? A nominal 20% reduction in transistor area need not deliver a 20% reduction in placed circuit area. Congestion can force extra spacing, buffering, or longer wires. The correct object of comparison is a routed block meeting timing and power constraints, accompanied by realistic manufacturing rules.

What would turn these modules into a manufacturing story

The next convincing evidence would connect local improvements to broad statistical behavior. Researchers would show distributions across a wafer and across lots, rather than only representative devices. They would track the relationship between backside alignment, contact resistance, leakage, and functional circuit performance. Reliability testing would examine sustained electrical stress and repeated temperature changes. Failure analysis would distinguish particles, incomplete isolation, mechanical damage during thinning, and variation in material growth, because each failure mode demands a different correction.

My engineering inference is that backside access and CFET stacking should be assessed together, even when their experiments are reported separately. The stack changes which terminals are hard to reach; backside processing changes which routes are available. Their benefits can reinforce each other, but their risks can also interact. The 2026 results are useful precisely because they expose specific bottlenecks that can be measured and improved. Progress here is a controlled reduction in unwanted resistance, variability, and process damage, followed by proof that the complete circuit retains those gains.

Wafer thinning creates another coupling between process steps. The substrate initially provides mechanical support; after substantial removal, the bonded carrier and remaining films help determine bow and stress. A contact mask aligned before bonding cannot assume that every point remains in exactly the same relative position afterward. This creates a feedback loop between mechanical metrology and electrical layout rules. A slightly larger alignment allowance may improve manufacturability while sacrificing some density, making the optimum a compromise that only integrated experiments can establish.